출판물 | 프로젝트 | 수상경력 | 학위논문
  출판물
Thesis
① Ph.D:  S.-I. Chae, "Defect detection and classification in VLSI pattern inspection," Stanford Univ., CA (USA), 1987.
② M.S:  S.-I. Chae, "Mtif and parameter analysis of reliability for the redundant digital system," Seoul National Univ., 1977.


International Journals & Thesis

[1] Kim, Tae Sung, et al. "Fast Integer Motion Estimation with Bottom-up Motion Vector Prediction for an HEVC Encoder." IEEE Transactions on Circuits and Systems for Video Technology(2017).
[2] S. Choi and S.-I. Chae, "Comparison of CABAC rate estimation models for HEVC rate distortion optimisation," Electronics Letters, vol. 50, pp. 441-442, 2014.
[3] G. Atwood, S.-I. Chae, and S. S. Shim, "Next-Generation Memory [Guest editors' introduction]," Computer, vol. 46, pp. 21-22, 2013.
[4] S.-M. Choi, J.-H. Kim, and S.-I. Chae, "Efficient test bitstream generation with an N-way covering algorithm for configurations of high-level syntax elements in video decoders," Consumer Electronics, IEEE Transactions on, vol. 59, pp. 592-597, 2013.
[5] D. Kim, K. Cha, D.-S. Hong, S. Choi, and S.-I. Chae, "A programmable video platform and its application mapping framework using the target application's systemC models," EURASIP Journal on Embedded Systems, vol. 2011, p. 5, 2011.
[6] J. Cho, S. Choi, and S.-I. Chae, "Constrained-random bitstream generation for H. 264/AVC decoder conformance test," Consumer Electronics, IEEE Transactions on, vol. 56, pp. 848-855, 2010.
[7] M. Koo and S.-I. Chae, "Flexible DMA subsystem in multi-core platforms for video applications," IEICE Electronics Express, vol. 7, pp. 1065-1071, 2010.
[8] S.-I. Han, S.-I. Chae, L. Brisolara, L. Carro, K. Popovici, X. Guerin, et al., "Simulink®-based heterogeneous multiprocessor SoC design flow for mixed hardware/software refinement and simulation," Integration, the VLSI Journal, vol. 42, pp. 227-245, 2009.
[9] K. Huang, X.-l. Yan, S.-i. Han, S.-i. Chae, A. A. Jerraya, K. Popovici, et al., "Gradual refinement for application-specific MPSoC design from Simulink model to RTL implementation," Journal of Zhejiang University SCIENCE A, vol. 10, pp. 151-164, 2009.
[10] J. Cho, D. Lee, S. Yoon, S. Park, and S.-I. Chae, "VLSI implementation of a VC-1 main profile decoder for HD video applications," IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol. 92, pp. 279-290, 2009.
[11] D. Kim. K. Cha, and S.-I. Chae, "Adaptive Scanline Filling Algorithm for OpenVG 2D Vector Graphics Accelerator," IEICE TRANSACTIONS on Information and Systems, vol. 92, pp. 1500-1502, 2009.
[12] D. Kim, K. Cha, and S.-I. Chae, "A high-performance OpenVG accelerator with dual-scanline filling rendering," Consumer Electronics, IEEE Transactions on, vol. 54, pp. 1303-1311, 2008.
[13] S. Park, D.-s. Hong, and S.-I. Chae, "A hardware operating system kernel for multi-processor systems," IEICE Electronics Express, vol. 5, pp. 296-302, 2008.
[14] S. Yoon, S.-I. Chae, "Cache optimization for H. 264/AVC motion compensation," IEICE transactions on information and systems, vol. 91, pp. 2902-2905, 2008.
[15] S.-I. Han, S.-I. Chae, L. Brisolara, L. Carro, R. Reis, X. Guérin, et al., "Memory-efficient multithreaded code generation from Simulink for heterogeneous MPSoC," Design Automation for Embedded Systems, vol. 11, pp. 249-283, 2007.
[16] S. Kim, and S.-I. Chae, "A bootstrapped switch for nMOS reversible energy recovery logic for low-voltage applications," IEICE transactions on electronics, vol. 89, pp. 649-652, 2006.
[17] E. Song, Y. Koo, Y.-J. Jung, D.-H. Lee, S. Chu, and S.-I. Chae, "A 0.25-μm CMOS quad-band GSM RF transceiver using an efficient LO frequency plan," Solid-State Circuits, IEEE Journal of, vol. 40, pp. 1094-1106, 2005.
[18] Y.-J. Jung, H. Jeong, E. Song, J. Lee, S.-W. Lee, D. Seo, et al., "A 2.4-GHz 0.25-μm CMOS dual-mode direct-conversion transceiver for bluetooth and 802.11 b," Solid-State Circuits, IEEE Journal of, vol. 39, pp. 1185-1190, 2004.
[19] E. Song, S.-W. Lee, J.-W. Lee, J. Park, and S.-I. Chae, "A reset-free anti-harmonic delay-locked loop using a cycle period detector," Solid-State Circuits, IEEE Journal of, vol. 39, pp. 2055-2061, 2004.
[20] Y. Ahn, D. Kim, S. Lee, S. Park, S. Yoo, K. Choi, S.-I. Chae, "An efficient simulation environment and simulation techniques for Bluetooth device design," Design automation for embedded systems, vol. 8, pp. 119-138, 2003.
[21] S. Lee, S.-I. Chae, “Two-step motion estimation algorithm for large search range using outlier pixel exclusion”, Electronics Letters, Volume 38, Issue 2, January 2002, p. 68 – 69
[22] Y. Shin, S.-I. Chae, and K. Choi, "Partial bus-invert coding for power optimization of application-specific systems," Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 9, pp. 377-383, 2001.
[23] J.-M. Kim, Y.-S. Shin, I.-G. Hwang, K.-S. Lee, S.-J. Han, S.-G. Park, and S.-I. Chae, "A high-performance videophone chip with dual multimedia VLIW processor cores," IEICE transactions on electronics, vol. 84, pp. 183-192, 2001.
[24] J. Lim, D.-G. Kim, and S.-I. Chae, "nMOS reversible energy recovery logic for ultra-low-energy applications," Solid-State Circuits, IEEE Journal of, vol. 35, pp. 865-875, 2000.
[25] S.-Y. Choi and S.-I. Chae, "Extended mean-distance-ordered search using multiple l 1 and l 2 inequalities for fast vector quantization," Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on, vol. 47, pp. 349-352, 2000.
[26] S.-Y. Choi, S.-I. Chae, and Y. S. Shim, "Rate-optimised motion estimation," Electronics Letters, vol. 36, pp. 1196-1197, 2000.
[27] J. Lim, D.-G. Kim, and S.-I. Chae, "A 16-bit carry-lookahead adder using reversible energy recovery logic for ultra-low-energy systems," Solid-State Circuits, IEEE Journal of, vol. 34, pp. 898-903, 1999.
[28] J. Lim, D.-G. Kim, and S.-I. Chae, "Reversible energy recovery logic circuits and its 8-phase clocked power generator for ultra-low-power applications," IEICE transactions on electronics, vol. 82, pp. 646-653, 1999.
[29] S.-Y. Choi and S.-I. Chae, "Hierarchical motion estimation in Hadamard transform domain," Electronics Letters, vol. 35, pp. 2187-2188, 1999.
[30] E. Song, S.-I. Chae, and W. Kim, "A 2 GHz CMOS downconverter with robust image rejection performance against the process variations," Journal of the Korean Physical Society, vol. 35, pp. S918-S926, 1999.
[31] A.M. Rassau, S.-I. Chae, K. Eshraghian, “Simple binary wavelet filters for efficient VLSI implementation”, Electronics Letters, Volume 35, Issue 7, p. 555 – 557, April 1999
[32] J. Lim, D.-G. Kim, S.-I. Chae, “Reduction in energy consumption by bootstrapped nMOS switches in reversible adiabatic CMOS circuits”, IEE Proceedings - Circuits, Devices and Systems, Volume 146, Issue 6, 1999 , p. 327 – 333
[33] S. Lee, J.-M. Kim, and S.-I. Chae, "New motion estimation algorithm using adaptively quantized low bit-resolution image and its VLSI architecture for MPEG2 video encoding," Circuits and Systems for Video Technology, IEEE Transactions on, vol. 8, pp. 734-744, 1998.
[34] J. Lim, K. Kwon, and S.-I. Chae, "Reversible energy recovery logic circuit without non-adiabatic energy loss," Electronics Letters, vol. 34, pp. 344-346, 1998.
[35] E.-W. Lee and S.-I. Chae, "Fast design of reduced-complexity nearest-neighbor classifiers using triangular inequality," Pattern Analysis and Machine Intelligence, IEEE Transactions on, vol. 20, pp. 562-566, 1998.
[36] Y. Shin, S.-I. Chae, and K. Choi, "Reduction of bus transitions with partial bus-invert coding," Electronics Letters, vol. 34, pp. 642-643, 1998.
[37] J.-M. Kim and S.-l. Chae, "A cost-effective architecture for HDTV video decoder in ATSC receivers," Consumer Electronics, IEEE Transactions on, vol. 44, pp. 1353-1359, 1998.
[38] K. Kwon and S.-I. Chae, "Simple reversible energy recovery logic using NMOS switch networks with crosscoupled PMOS pair," Electronics Letters, vol. 34, pp. 2215-2216, 1998.
[39] E.-W. Lee and S.-I. Chae, "Error-driven edge selection for ΣΔ modulated signals to suppress in-band noise due to non-uniform sampling," Electronics Letters, vol. 34, pp. 618-619, 1998.
[40] S.-Y. Choi, and S.-I. Chae, “Incremental-search fast vector quantiser using triangular inequalities for multiple anchors “, Electronics Letters, Volume 34, Issue 12, p. 1192 – 1193, June 1998
[41] S. Lee, S.-I. Chae, “Motion estimation algorithm using low resolution quantisation”, Electronics Letters, Volume 32, Issue 7, p. 647 – 648, March 1996
[42] S. Park, J. Lim, and S.-I. Chae, "Discrete-time cellular neural networks using distributed arithmetic," Electronics Letters, vol. 31, pp. 1851-1852, 1995.
[43] K. Na, S.-I. Chae, and S. Ann, "Modified delta coding algorithm for real parameter optimisation," Electronics Letters, vol. 31, pp. 1169-1171, 1995.
[44] E.-w. Lee and S.-I. Chae, "New perceptron model using random bitstreams," Neural computation, vol. 7, pp. 280-283, 1995.
[45] S.-J. Min and S.-I. Chae, "Neural network implementation using new pulse arithmetic," International journal of electronics, vol. 77, pp. 1015-1024, 1994.
[46] S.-I. Chae, J. T. Walker, C.-c. Fu, and R. F. Pease, "Content-addressable memory for VLSI pattern inspection," Solid-State Circuits, IEEE Journal of, vol. 23, pp. 74-78, 1988.
[47] J. Walker, S.-I. Chae, S. Shapiro, and R. S. Larsen, "Microstore-The Stanford Analog Memory Unit," Nuclear Science, IEEE Transactions on, vol. 32, pp. 616-621, 1985.


International Conferences

[1] D.-T. Nghia, T.-S. Kim, H.-J. Lee, and S.-I. Chae, "A Modified TZ Search Algorithm for Parallel Integer Motion Estimation in High Efficiency Video Coding," 12th International SoC Design Conference (accepted for publication)
[2] J. Cui, Y. Choi, and S.-I. Chae, “Coding Efficiency of AVS 2.0 for CBAC and CABAC Engines,” in ICAIP 2015, 2015
[3] S. Roe, S. Choi, W. Jung, and S.-I. Chae, “Reduction of the Computational Redundancy in Integer Motion Estimation using a Modified Test Zone Search Algorithm in HEVC,” in ICEIC 2015, 2015
[4] H. Jung, S. Choi, and S.-I. Chae, "Coding efficiency of the context-based arithmetic coding engine of AVS 2.0 in the HEVC encoder," in Consumer Electronics (ICCE), 2015 IEEE International Conference on, pp. 377-378, 2015
[5] D. Hong and S.-I. Chae, "Efficient test bitstream generation method for verification of HEVC decoders," in Consumer Electronics (ISCE 2014), The 18th IEEE International Symposium on, pp. 1-2, 2014
[6] S. Choi, S. Jeoung, J. Kim, and S.-I. Chae, "Generation of efficient bitstreams for functional tests of video decoders," in Consumer Electronics (ICCE), 2013 IEEE International Conference on, pp. 566-567, 2013
[7] S. Choi, J. J. Park, M. Koo, D. Kim, and S.-I. Chae, "A 40 Mbps H. 264/AVC CAVLC decoder using a 64-bit multiple-issue video parsing coprocessor," in SOC Conference (SOCC), 2010 IEEE International, pp. 105-108, 2010
[8] D. Kim, K. Cha, S. Choi, and S.-I. Chae, "Configurable high-performance video platform using multiple RISC clusters connected with separated data and control networks," in Signal Processing Systems, 2009. SiPS 2009. IEEE Workshop on, pp. 173-178, 2009
[9] K. Cha, D. Kim, and S.-I. Chae, "an optimized rendering algorithm for hardware implementation of openVG 2D vector graphics," in SoC Design Conference, 2008. ISOCC'08. International, pp. I-338-I-341, 2008
[10] M. Koo and S.-I. Chae, "High performance IPC hardware accelerator and communication network for MPSoCs," in International SoC Design Conference, Vol.3 CDC Session pp.21-22, IEEE, Nov. 2008.
[11] K. Huang, S.-i. Han, K. Popovici, L. Brisolara, X. Guerin, L. Li, et al., "Simulink-based MPSoC design flow: case study of Motion-JPEG and H. 264," in Design Automation Conference, 2007. DAC'07. 44th ACM/IEEE, pp. 39-42, 2007
[12] M. Koo and S.-I. Chae, "Hardware implementation of inter-processor communication in MPSoCs for multimedia applications," ITC-CSCC: 2007, pp. 825-826, 2007.
[13] J. Cho, D. Lee, S. Park, and S. Chae, "A Hybrid Verification Methodology for SoCBase-DE Design Flow," ITC-CSCC: 2007, pp. 957-958, 2007.
[14] S.-I. Han, X. Guerin, S.-I. Chae, and A. A. Jerraya, "Buffer memory optimization for video codec application modeled in Simulink," in Proceedings of the 43rd annual Design Automation Conference, pp. 689-694, 2006
[15] R. Huang and S.-I. Chae, "Implementation of an OpenVG rasterizer with configurable anti-aliasing and multi-window scissoring," in Computer and Information Technology, 2006. CIT'06. The Sixth IEEE International Conference on, pp. 179-179, 2006
[16] S.-I. Han, S.-I. Chae, and A. A. Jerraya, "Functional modeling techniques for efficient SW code generation of video codec applications," in Proceedings of the 2006 Asia and South Pacific Design Automation Conference, pp. 935-940, 2006
[17] S. Park, S. Yoon, and S.-I. Chae, "Reusable component IP design using refinement-based design environment," in Design Automation, 2006. Asia and South Pacific Conference on, pp. 6, 2006
[18] S. Park, S. Yoon, and S.-I. Chae, "A mixed-level virtual prototyping environment for refinement-based design environment," in Rapid System Prototyping, 2006. Seventeenth IEEE International Workshop on, pp. 63-68, 2006
[19] S. Yoon, S. Park, and S.-I. Chae, "Implementation of a H. 264 decoder with Template-based Communication Refinement," in IEEE Asia-Pacific conference on Circuits and Systems (APCCAS 2006), pp.571-574, Dec 2006.
[20] R. Huang and S.-i. Chae, "An OpenVG-Compliant Vector Graphics Accelerator," in ISOCC 2006 Conference,  pp. 648-649, 2006
[21] M. Kim, I. Hwang, and S.-I. Chae, "A fast VLSI architecture for full-search variable block size motion estimation in MPEG-4 AVC/H. 264," in Proceedings of the 2005 Asia and South Pacific Design Automation Conference, pp. 631-634, 2005
[22] S. Park and S.-I. Chae, "AC/C++-based functional verification framework using the SystemC verification library," in Rapid System Prototyping, 2005.(RSP 2005). The 16th IEEE International Workshop on, pp. 237-239, 2005
[23] S. Kim and S.-I. Chae, "Implementation of a simple 8-bit microprocessor with reversible energy recovery logic," in Proceedings of the 2nd conference on Computing frontiers, pp. 421-426, 2005
[24] S. Kim and S.-I. Chae, "Complexity reduction in an nRERL microprocessor," in Proceedings of the 2005 international symposium on Low power electronics and design, pp. 180-185, 2005
[25] S. Park and S.-I. Chae, "A two-week program for a platform-based SoC design," in Microelectronic Systems Education, 2005.(MSE'05). Proceedings. 2005 IEEE International Conference on, pp. 43-44, 2005
[26] N. Sreedhar and S.-I. Chae, "System level architecture design," in with EDA Technofair Design Automation Conference Asia and South Pacific: Proceedings of the 2005 conference on Asia South Pacific design automation, 2005.
[27] S.-I. Han, A. Baghdadi, M. Bonaciu, S.-I. Chae, and A. A. Jerraya, "An efficient scalable and flexible data transfer architecture for multiprocessor SoC with massive distributed memory," in Proceedings of the 41st annual Design Automation Conference, pp. 250-255, 2004
[28] S. Kwon, E. Song, and S.-I. Chae, "An Integrated Cycle-Accurate Energy Measurement Circuit for CMOS VLSI Systems," in ISOCC 2004 Conference, pp. 35-36, 2004
[29] E. Song, Y.-K. Park, S. Kwon, and S.-I. Chae, "A cycle-accurate energy estimator for CMOS digital circuits," in Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, ed: Springer, pp. 159-168, 2004
[30] E. Song, I.-C. Choi, Y.-K. Park, and S.-I. Chae, "A cycle-accurate joulemeter for CMOS VLSI circuits," in Solid-State Circuits Conference, 2003. ESSCIRC'03. Proceedings of the 29th European, pp. 619-622, 2003
[31] S. Kim, J.-H. Kwon, and S.-I. Chae, "An 8-b nRERL microprocessor for ultra-low-energy applications," in Proceedings of the 2001 Asia and South Pacific Design Automation Conference, pp. 27-28, 2001
[32] J.-W. Shin, S.-I. Chae, Y. M. Sook, and D.-S. Park, "Region-growing approach to detect microcalcifications in digital mammograms," in Multispectral Image Processing and Pattern Recognition, pp. 64-68, 2001
[33] S.-W. Lee, K.-Y. Lee, E. Song, Y.-J. Jung, H. Jeong, J.-M. Kim, S.-I. Chae, et al., "A single-chip 2.4 GHz direct-conversion CMOS transceiver with GFSK modem for Bluetooth application," in VLSI Circuits, 2001. Digest of Technical Papers. 2001 Symposium on, 2001, pp. 245-246, 2001
[34] J.-H. Kwon, J. Lim, and S.-I. Chae, "A three-port nRERL register file for ultra-low-energy applications," in Proceedings of the 2000 international symposium on Low power electronics and design, pp. 161-166, 2000
[35] K.-s. Oh, S.-y. Yoon, and S.-I. Chae, "Emulator environment based on an FPGA prototyping board," in Rapid System Prototyping, 2000. RSP 2000. Proceedings. 11th International Workshop on, pp. 72-77, 2000
[36] K. Nose, S.-I. Chae, and T. Sakurai, "Voltage dependent gate capacitance and its impact in estimating power and delay of CMOS digital circuits with low supply voltage (poster session)," in Proceedings of the 2000 international symposium on Low power electronics and design, pp. 228-230, 2000
[37] E.-S. Song, S.-I. Chae, and W. Kim, "A 2 GHZ CMOS double conversion downconverter with robust image rejection performance against the process and temperature variations," in VLSI Circuits, 2000. Digest of Technical Papers. 2000 Symposium on, pp. 38-41, 2000
[38] J. Lim, D.-G. Kim, S.-C. Kang, and S.-I. Chae, "An 8× 8 nRERL serial multiplier for ultra-low-power aplications," in Proceedings of the 2000 Asia and South Pacific Design Automation Conference, pp. 35-36, 2000
[39] K. Na, K. J. Lee, and S.-I. Chae, "Frequency-domain separation of convolved non-stationary signals with adaptive non-causal FIR filters," in Signal Processing Conference, 2000 10th European, pp. 1-4, 2000
[40] K. Na, S.-C. Kang, K. Lee, and S.-i. Chae, "Frequency-Domain Implementation of Block Adaptive Filters for ICA-Based Multichannel Blind Deconvolution," in Proc. ICASSP, 1999.
[41] K. Na, S. Kang, K. Lee, and S.-I. Chae, "Frequency-domain implementation of block adaptive filters for ICA-based multichannel blind deconvolution+ I3055," 1999.
[42] Y. Shin, S.-I. Chae, and K. Choi, "Partial bus-invert coding for power optimization of system level bus," in Proceedings of the 1998 international symposium on Low power electronics and design, pp. 127-129, 1998
[43] S. Lee and S.-I. Chae, "New motion estimation algorithm and its block-matching criteria using low-resolution quantization," in International Technical Conference on circuits/Systems, Computers and Communications, pp. 175-182, Aug 1998.
[44] E. Lee and S.-I. Chae, "Analysis of the non-uniform samplings in sigma-delta modulated signals," in ISCAS ’97, May 1998.
[45] E.-W. Lee and S.-I. Chae, "Analysis of non-uniform sampling effects in sigma-delta modulated signals," in Circuits and Systems, 1998. ISCAS'98. Proceedings of the 1998 IEEE International Symposium on, pp. 377-380, 1998
[46] K. Na and S.-I. Chae, "An HMM/MLP hybrid approach for improving discrimination in speech recognition," in Neural Networks Proceedings, 1998. IEEE World Congress on Computational Intelligence. The 1998 IEEE International Joint Conference on, pp. 156-159 vol.1, 1998
[47] S. Park, J. Lim, and S.-I. Chae, "Digital Implementation of discrete-time cellular neural networks with distributed arithmetic," in Neural Networks, 1997., International Conference on, pp. 959-963, 1997
[48] K. Na and S.-I. Chae, "Single-sensor active noise cancellation using recurrent neural network predictors," in Neural Networks, 1997., International Conference on, pp. 2153-2156, 1997
[49] S. Park and S.-I. Chae, "Improved sufficient convergence condition for the discrete-time cellular neural networks," in Neural Networks, 1997., International Conference on, pp. 1158-1161, 1997
[50] J.-M. Kim and S.-I. Chae, "New MPEG2 decoder architecture using frequency scaling," in Circuits and Systems, 1996. ISCAS'96., Connecting the World., 1996 IEEE International Symposium on, pp. 253-256, 1996
[51] S. Lee and S.-I. Chae, "Two-step motion estimation algorithm using low-resolution quantization," in Image Processing, 1996. Proceedings., International Conference on, pp. 795-798, 1996
[52] S. Lee, J. M. Kim, and S.-I. Chae, "New motion estimation using low-resolution quantization for MPEG2 video encoding," in VLSI Signal Processing, IX, 1996.,[Workshop on], pp. 428-437, 1996
[53] S.-Y. Choi and S.-I. Chae, "Fast vector quantizer using multiple sorted index tables," in Image Processing, 1996. Proceedings., International Conference on, pp. 443-446, 1996
[54] K. Na and S.-I. Chae, "GPD training of the state weighting functions in hidden control neural network," in Acoustics, Speech, and Signal Processing, 1996. ICASSP-96. Conference Proceedings., 1996 IEEE International Conference on, pp. 3366-3369, 1996
[55] K. Na, B. Jeon, D.-I. Chang, S.-I. Chae, and S. Ann, "Discriminative training of hidden Markov models using overall risk criterion and reduced gradient method," in Fourth European Conference on Speech Communication and Technology, 1995.
[56] J.-M. Kim, S.-K. Hong, E.-W. Lee, and S.-I. Chae, "Multithread video coding processor for the videophone," in VLSI Signal Processing, VIII, 1995. IEEE Signal Processing Society [Workshop on], pp. 470-480, 1995
[57] K. Na, J. Ryu, D.-I. Chang, S.-I. Chae, and S. Ann, "Recurrent neural prediction models for speech recognition," in Fourth European Conference on Speech Communication and Technology, 1995.
[58] J. Lim and S.-I. Chae, "Ratio pulse arithmetic for radial basis function network," in Neural Networks, 1995. Proceedings., IEEE International Conference on, pp. 1492-1495, 1995
[59] K. Na, S.-I. Chae, and S. Ann, "Corrective training of hidden control neural network," in Neural Networks, 1995. Proceedings., IEEE International Conference on, pp. 2867-2870, 1995
[60] E.-W. Lee and S.-I. Chae, "New classifier with reduced computational complexity," in Neural Networks, 1995. Proceedings., IEEE International Conference on, pp. 968-973, 1995
[61] E.-W. Lee and S.-I. Chae, "Quasi-Isometry and Its Application to Neural Networks: Estimation of the Minimal Feature Space Dimension," in World Congress on Neural Networks, 1995.
[62] S. J. Park, J. H. Lim, and S. I. Chae, "IMPLEMENTATION OF THE RECONFIGURABLE DISCRETE-TIME CELLULAR NEURAL NETWORKS," in ICVC: International Conference on VLSI and CAD  vol. 4, pp. 51-54, 1995
[63] E. W. Lee and S. I. Chae, "Digit Recognition with Slant Regularization," in ICONIP: International Conference On Neural Information Processing, vol. 1, pp. 511-516, 1994
[64] S. Park, S.-J. Min, and S.-I. Chae, "Stereo correspondence with discrete-time cellular neural networks," in Circuits and Systems, 1994. ISCAS'94., 1994 IEEE International Symposium on, pp. 225-228, 1994
[65] S.-J. Min, E.-W. Lee, and S.-I. Chae, "A study on the stochastic computation using the ratio of one pulses and zero pulses," in Circuits and Systems, 1994. ISCAS'94., 1994 IEEE International Symposium on, pp. 471-474, 1994
[66] J. Lim, E. Lee, and S.-I. Chae, "Character recognition by neural networks with single-layer training and rejection mechanism," in Circuits and Systems, 1994. ISCAS'94., 1994 IEEE International Symposium on, pp. 327-330, 1994
[67] E.-W. Lee, J.-H. Won, and S.-I. Chae, "Modified probabilistic RAM architecture for VLSI implementation of a backpropagation learning algorithm," in Circuits and Systems, 1993., ISCAS'93, 1993 IEEE International Symposium on, pp. 1897-1900, 1993
[68] S. J. Park, C. G. Kim, and S. I. Chae, "A VLSI Design of the Neural Networks using Random Pulse Streams," in JTC-CSCC: Joint Technical Conference on Circuits Systems, Computers and Communications, pp. 501-503, 1992
[69] J. Suh and S.-I. Chae, "A Backpropagation Algorithm for Neural Networks Using Random Pulse Streams," in Artificial Neural Networks, 2: Proceedings of the 1992 International Conference on Artificial Neural Networks (ICANN-92), Brighton, United Kingdom, 4-7 September 1992, p. 1035, 1992
[70] J. W. Suh and S. I. Chae, "Error Analysis in the Digital Implementation Using Random Pulse Train," in JTC-CSCC: Joint Technical Conference on Circuits Systems, Computers and Communications, pp. 34-37, 1991
[71] S. I. Chae, "POWER-BUS NOISE CONTROL FOR HIGH-SPEED CMOS VLSI CIRCUITS," in ICVC: International Conference on VLSI and CAD , vol. 1, pp. 129-132, 1989
[72] S.-I. Chae, J. T. Walker, C.-C. Fu, and R. F. Pease, "Defect Detection And Classification Using The Euler Number," in 1988 Microlithography Conferences, pp. 432-439, 1988
[73] S.-I. Chae, J. T. Walker, D. H. Dameron, C.-C. Fu, and J. D. Meindl, "Template-Set Approach to VLSI Pattern Inspection," in Cambridge Symposium_Intelligent Robotics Systems, pp. 136-144, 1987


Domestic Journals

[1] 최승민, 채수익, "로봇을 위한 운영체제 수준의 동적 전력 관리," 전자공학회논문지-SD, vol. 42, pp. 63-72, 2005.
[2] 신영수, 채수익, 최기영, "부분 버스 반전 부호화를 이용한 시스템 수준 전력 최적화", 전자공학회논문지, vol. 31-C no. 12 pp.23-30, 1998
[3] 김천곤, 이일완, 채수익, "Ringing 상쇄기능이 있는 저잡음 출력 버퍼", 전자공학회논문지, vol. 34 no. 4 pp.0-0, 1997
[4] 이일완, 채수익, "거리근사를 이용하는 고속 최근 이웃 탐색 분류기에 관한 연구", 전자공학회논문지, vol. 34 no. 2 pp.71-79, 1997
[5] 김천곤, 이일완, 채수익, "Ringing 상쇄 기능이 있는 저잡음 출력버퍼 (Low-noise Output Buffer with ringing cancelation)," 전자공학회논문지-C, vol. 34, pp. 209-215, 1997.
[6] 이일완, 채수익, "거리 근사를 이용하는 고속 최근 이웃 탐색 분류기에 관한 연구 (Study on the Fast Nearest-Neighbor Searching Classifier Using Distance Approximation)," 전자공학회논문지-C, vol. 34, pp. 135-143, 1997.
[7] 오규환, 채수익, "초기 일반 지식을 갖고 있는 점증 적응 학습 알고리듬 (Incremental Adaptive Learning Algorithm with Initial Genetic Knowledge)," 전자공학회논문지-B, vol. 33, pp. 387-396, 1996.
[8] 이성수, 채수익, "저해상도 양자화된 이미지를 이용하여 연산량을 줄인 움직임 추정 기법 (A Motion Estimation Algorithm with Low Computational Cost Using Low-resolution Quantized Image)," 전자공학회논문지-B, vol. 33, pp. 1285-1292, 1996.
[9] 김정민, 홍석균, 이일완, 채수익, "동영상 전화기용 다중 스레드 비디오 코딩 프로세서 (Multithread Video Coding Processor for the Videophone)," 전자공학회논문지-A, vol. 33, pp. 883-892, 1996.
[10] 박성준, 임준호, 채수익, "분산 연산 방식을 이용한 이산시간 cellular 신경회로망의 하드웨어 구현", 전자공학회논문지, vol. 33 no. 1 pp.153-160, 1996
[11] 박성준, 임준호, 채수익, "분산연산 방식을 이용한 이산시간 Cellular 신경회로망의 하드웨어 구현 (Hardware Implementation of Discrete-Time Cellular Neural Networks Using Distributed Arithmetic)," 전자공학회논문지-B, vol. 33, pp. 153-160, 1996.
[12] 임준호, 김정민, 채수익, "영상처리 프로세서의 기술과 동향", 정보과학회논문지, vol. 14 no. pp.27-40, 1996
[13] 남기철, 채수익, "단위 처리기를 조기 은퇴시키는 완전탐색 블록정합 알고리듬 (A Full-Search Block-Matching Algorithm with Early Retirement of Processing Elements)," 전자공학회논문지-B, vol. 32, pp. 1417-1423, 1995.
[14] 임준호, 채수익, "단층 신경망과 이중 기각 방법을 이용한 문자인식 (Single-Layer Neural Networks with Double Rejection Mechanisms for Character Recognition)," 전자공학회논문지-B, vol. 32, pp. 522-532, 1995.
[15] 이일완, 채수익, "확률 연산을 이용한 볼츠만 머신 (Boltzmann machine using Stochastic Computation)," 전자공학회논문지-A, vol. 31, pp. 786-795, 1994.
[16] 원재희, 채수익, "pRAM 회로망을 위한 역전파 학습 알고리듬 (A Backpropagation Learning Algorithm for pRAM Networks)," 전자공학회논문지-B, vol. 31, pp. 107-114, 1994.
[17] 민승재, 채수익, "펄스열에서 1 인 펄스수와 0 인 펄스수의 비를 이용하여 확률연산을 하는 신경회로망 (A Neural Network Based on Stochastic Computation Using the Ratio of the Number of Ones and Zeros in the Pulse Stream)," 전자공학회논문지-B, vol. 31, pp. 1020-1027, 1994.
[18] 박성준, 채수익, "국소적인 연결을 갖는 신경회로망을 이용한 스테레오 정합 (Steropsis with Cellular Neural Networks)," 전자공학회논문지-B, vol. 31, pp. 1888-1895, 1994.
[19] 고명삼, 채수익, "MTIF and Parameter Analysis of Reliability for the Redundant Digital System," 전기공학회지, vol. 28, pp. 60-66, 1979.


Domestic Conferences

[1] 원의연, 채수익, "HEVC 인트라 인코더를 위한 RDO 알고리듬의 개선," 2013 년도 한국방송공학회 하계 학술대회, pp. 123-126, 2013.
[2] 김지천, 채수익, "CUDA 를 이용한 HEVC 인루프 필터의 병렬화 구현," 2012 년도 대한전자공학회 하계종합학술대회, pp. 1149-1152, 2012.
[3] 정승규, 최순우, 채수익, "MPEG-4 디코더의 디버깅 및 검증을 위한 비트스트림 생성," 2012 년도 대한전자공학회 하계종합학술대회, pp. 93-96, 2012.
[4] 차길형, 홍도선, 채수익, "1080p H.264/AVC 프로그래머블 움직임 보상 엔진의 설계", 한국반도체학술대회, pp.305-306, 2012
[5] 유성목, 채수익, "Application-Specific Instruction Processor 구조의 1080p 급 H. 264/AVC 디블로킹 필터 설계," 2011 년도 대한전자공학회 추계종합학술대회, pp. 149-150, 2011.
[6] 최순우, 조문성, 채수익, "H.264 인트라 인코더의 성능 향상을 위한 고속 예측 모드 결정 방법", 대한전자공학회 추계학술대회, pp.156-157, 2011
[7] 김지천, 최순우, 채수익, "H. 264 복호기 검증을 위한 효율적인 테스트 비트스트림 선택 알고리듬," 2011 년도 대한전자공학회 추계종합학술대회, pp. 151-152, 2011.
[8] 박종규, 최순우, 채수익, "VLIW ASIP 의 Instruction Set Architecture 설계 환경과 이를 이용해 설계한 H. 264 CABAC Decoder," 대한전자공학회 2011 년 SoC 학술대회, pp. 365-369, 2011.
[9] 안준환, 오적, 최기영, 채수익, "LatticeMico32 프로세서를 위한 맞춤 명령어 자동 생성기의 설계," 대한전자공학회 2011 년 SoC 학술대회, pp. 145-148, 2011.
[10] 홍도선, 최근재, 채수익, "LM32 RISC 코어 기반 멀티코어 시스템에서 MJPEG의 멀티쓰레딩 실험", 한국반도체학술대회, pp.339-340, 2011
[11] 구문모, 홍도선, 최근재 ; 채수익, "고성능 비디오 응용을 위한 processor cluster 아키텍쳐 ", 한국반도체학술대회, pp.377-378, 2011
[12] 차길형, 김대웅, 최순우 ; 채수익, "리스크 클러스터 기반의 고성능 비디오 플랫폼을 이용한 H.264/AVC high-profile 720p 디코더의 설계", 한국반도체학술대회, pp.341-342, 2011
[13] 최순우, 차길형, 채수익, "명령어 버퍼를 사용하여 프로시저 호출과 루프의 분기 오버헤드를 제거하는 방법," 대한전자공학회 2010 년 정기총회 및 추계종합학술대회, pp. 455-456, 2010.
[14] 조문성, 손은용, 채수익, "H. 264/AVC Intra Encoder 를 위한 Application-specific instruction-set processor (ASIP) 설계," 2010 년도 대한전자공학회 하계종합학술대회, pp. 778-779, 2010.
[15] 김대웅, 차길형, 최순우 ; 손은용 ; 채수익, "High-Definition multiprocessor video platform", SoC 학술대회, 2010
[16] 최순우, 차길형, 손은용 ; 김대웅 ; 채수익, "멀티 포맷 디코더를 위한 테이블 매칭 알고리즘", SoC 학술대회, 2010
[17] 최근재, 홍도선, 채수익, "OpenRISC 클러스터를 이용한 MJPEG 디코더의 최적화," 대한전자공학회 2010 년 정기총회 및 추계종합학술대회, pp. 91-92, 2010.
[18] 홍도선, 최근재, 채수익, "ASIP 명령어집합 선택을 위한 성능 추정 방법," 대한전자공학회 2010 년 정기총회 및 추계종합학술대회, pp. 65-66, 2010.
[19] 손은용, 채수익, "Local memory access 를 최소화하는 VC-1 Overlap Smoothing & In loop Deblocking 구조 탐색," 대한전자공학회 2009 년 정기총회 및 추계종합학술대회, pp. 59-60, 2009.
[20] 손은용, 김대웅, 채수익, "VC-1 overlap smoothing과 In loop deblocking의 최적 구조 탐색", CEIC(conference on electronics and information communication), 2009.
[21] 최근재, 홍도선, 채수익, "오픈소스 프로세서들의 드라이스톤 MIPS 측정 결과 비교," 대한전자공학회 2009 년 정기총회 및 추계종합학술대회, pp. 61-62, 2009.
[22] 최순우, 조진현, 박상규, 채수익, "템플릿 기반 디자인을 위한 Channel RTL 생성," 2008 년도 SOC 학술대회, pp. 355-358, 2008.
[23] 이두원, 조진현, 윤상용, 박상규, 채수익, "A high performance VC-1 decoder", 한국반도체 학술대회 논문집, 2008
[24] 최영규, 이창현, 채수익, "H.264/AVC 움직임 보상의 데이터 리드 사이클의 최소화를 위한 SDRAM 구성", 한국반도체 학술대회 논문집, pp.915-916, 2006
[25] 김수형, 박상규, 채수익, "MPSoC simulation platform based on MPI", 한국반도체 학술대회 논문집, pp.331-332, 2006
[26] 이세희, 박상규, 채수익, "Wichbone 버스 기반의 SoC 개발을 위한 기능 검증 환경 구현", 한국반도체 학술대회 논문집, pp.345-346, 2006
[27] 김선겸, 박영길, 최인찬, 송은석, 최기영, 채수익, "A single-chip, high-speed cycle-accurate energy measurement circuits", IDEC Conference, pp.43-46, 2003
[28] 박영길, 최인찬, 송은석, 채수익, "Voltage dependency of CMOS load capacitance and its effect on estimating energy consumed in CMOS digital circuits", IDEC Conference, pp.35-38, 2003
[29] 최인찬, 송은석, 박영길, 채수익, "CMOS 집적회로의 단위 사이클별 소모 에너지 모델링", CAD 및 VLSI 설계 연구회 학술 발표회 논문집, pp.115-120, 2003
[30] 이평우, 최선영, 채수익, "배터리 수명을 연장시키기 위한 스텝 모터 제어 방법", CAD 및 VLSI 설계 연구회 학술 발표회 논문집, pp.198-203, 2003
[31] 윤상용, 조한수, 채수익, "FIFO based PCI interface for Co-simulation", SOC Design Conference, 2002
[32] Y. Ahn, D. Kim, S. Lee, S. Park, S. Yoo, K. Choi, S. Chae, "An fficient simulation environment and simulation techniques for Bluetooth device design," Design automation for embedded systems, vol. 8, pp. 119-138, 2003.
[33] Y. Ahn, D. Kim, S. Lee, S. Park, S. Yoo, K. Choi, S.-I. Chae, "An Efficient Simulation Environment for the Design of Networked Bluetooth Devices," SoC Design Conference 대한전자공학회 기타 간행물, pp. 622-628, 2001.
[34] 김석기, 권준호, 채수익, "8b nRERL microprocessor using energy-efficient clocked power generator", IDEC Conference, pp.220-222, 2001
[35] 이경진, 송은석, 채수익, "CMOS active pixel sensor array integrated with wavelet-based image processor", IDEC Conference, pp.212-213, 2001
[36] 정재헌, 채수익, "에너지 실측을 기반으로한 저전력 운영체제의 구현," ICCAS 2001, pp. 2351-2353, 2001.
[37] 송은석, 채수익, "CMOS active pixel sensor with enhanced fill factor", IDEC Conference, pp.214-215, 2001
[38] 채수익, 김성용, 최현, 박동선, "신속한 호 설정을 위한 위한 확장된 SIP 구조 제안," 2001 년도 추계학술발표논문집, pp. 51-55, 2001.
[39] 나경민, 이경진, 채수익, "완전 연결된 피드백 구조를 이용한 주파수 영역 신호 분리", 한국뇌학회 학술대회, pp.49-49, 2000
[40] 민병준, 채수익, 이상백, 박동선, "H. 323 기반 인터넷 폰의 부가 서비스를 위한 향상된 구조 설계," 대한전자공학회 종합 학술 대회 논문집 (추계) 2000, Vol. 3: 컴퓨터 그룹 Vol. 23 No. 2, pp. 133-136, 2000.
[41] 조덕연, 박태진, 김응수, 채수익, "자기학습 확률 신경회로망", JCEANF, pp.196-200, 1999
[42] 나경민, 채수익, "독립성분분석을 위한 점수 함수에 관한 연구", JCEANF, pp.42-48, 1999
[43] 임준호, 권기백, 채수익, "초저전력 가역에너지복원 논리회로," 대한전자공학회 학술대회 논문집 (한국반도체 대한전자공학회 학술대회 논문집) 제 5 권, vol. 5, pp. 427-430, 1998.
[44] 권기백, 채수익, "단열 스위칭에 의한 소모 에너지의 분석," 대한전자공학회 학술대회 논문집 (한국반도체 대한전자공학회 학술대회 논문집) 제 5 권, vol. 5, pp. 441-442, 1998.
[45] 권기백, 배준우, 채수익, "단열 회로를 이용한 TFT-LCD 용 게이트 드라이버의 설계 (Design of TFT-LCD Gate Driver Utilizing the Adiabatic Circuit)," 대한전자공학회 학술대회 논문집 제 20 권 1 호, vol. 20, pp. 695-698, 1997.
[46] 이일완, 채수익, "부분 패턴 정합을 이용한 문서 압축 방법 (Document Compression Method using Partial Pattern Matching)," 한국통신학회 학술발표회 논문집 (정보기술분야), pp. 523-528, 1997.
[47] 김천곤, 채수익, "Ringing 상쇄 기능을 가진 저잡음 출력 버퍼", 대한전자공학회 학술회의, pp.363-366, 1996
[48] 나경민, 채수익, "평탄화된 사후확률을 이용한 HMM의 학습", FAN 인공지능, 신경망 및 퍼지시스템, pp.64-69, 1996
[49] 오규환, 채수익, "초기 일반 지식을 갖고 있는 경쟁 학습 신경 회로망의 구현", 인공지능, 신경망 및 퍼지시스템 종합 학술대회 논문집, pp.126-131, 1995
[50] 김정민, 홍석균, 이일완, 채수익, "동영상 전화기용 multi-threading video coding processor의 설계", DSP WORKSHOP, pp.153-157, 1995
[51] 이일완, 채수익, "분류기의 계산복잡도를 줄이는 방법에 관한 연구", 인공지능, 신경망 및 퍼지시스템 종합 학술대회 논문집, pp.149-154, 1995
[52] 민승재, 채수익, "새로운 펄스연산방법을 이용한 Hopfield Network 의 구현 (Hopfield Network Implementation Using New Pulse Arithmetic)," 대한전자공학회 학술대회 (FAN 춘계종합학술대회), pp. 385-390, 1994.
[53] 이일완, 채수익, "Boltzmann Machine using Stochastic Computation and its Applications to Digit Recognition," 대한전자공학회 학술발표회 논문집 (인공지능/신경망/퍼지관련), pp. 182-185, 1993.
[54] 임준호, 이일완, 채수익, "HyLCAM 을 이용한 숫자인식에 관한 연구 (A Study on Digit Recognition Using HyLCAM)," 대한전자공학회 학술대회 논문집 (인공지능/신경망/퍼지시스템) 제 3 권, vol. 3, pp. 495-499, 1993.
[55] E. W. Lee and S. I. Chae, "An Alternative RPT Neuron Model: Introducing a Nonlinearity into RPT Neuron Model," 대한전자공학회 학술대회 논문집 (인공지능/신경망/퍼지시스템) 제 2 권, vol. 2, pp. 530-535, 1992.
[56] 윤인수, 채수익, "Testability 를 높이기 위한 Sea-of-Gates 구조에 관한 연구 (A Study on the Sea-of-Gates Structure to Enhance Testability)," 대한전자공학회 학술발표회 논문집 (회로/시스템연구회) 제 14 권 1 호, vol. 14, pp. 85-88, 1992.
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